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ltc2601/ltc2611/ltc2621 1 2601fb typical application description 16-/14-/12-bit rail-to-rail dacs in 10-lead dfn the ltc ? 2601/ltc2611/ltc2621 are single 16-, 14- and 12-bit, 2.5v-to-5.5v rail-to-rail voltage output dacs in a 10-lead dfn package. they have built-in high performance output buffers and are guaranteed monotonic. these parts establish new board-density benchmarks for 16- and 14-bit dacs and advance performance standards for output drive and load regulation in single-supply, volt- age-output dacs. the parts use a simple spi/microwire compatible 3-wire serial interface which can be operated at clock rates up to 50mhz. daisy-chain capability, hardware clr and asyn- chronous dac update ( ldac ) pins are included. the ltc2601/ltc2611/ltc2621 incorporate a power-on reset circuit. during power-up, the voltage outputs rise less than 10mv above zero scale until a valid write and update take place. the power-on reset circuit resets the ltc2601-1/ltc2611-1/ltc2621-1 to midscale. the volt- age outputs stay at midscale until a valid write and update take place. l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5396245. features applications n smallest pin-compatible single dacs: ltc2601: 16 bits ltc2611: 14 bits ltc2621: 12 bits n guaranteed monotonic over temperature n wide 2.5v to 5.5v supply range n low power operation: 300a at 3v n power down to 1a, max n high rail-to-rail output drive (15ma, min) n double-buffered data latches n asynchronous dac update pin n ltc2601-1/ltc2611-1/ltc2621-1: power-on reset to midscale n tiny (3mm 3mm) 10-lead dfn package n mobile communications n process control and industrial automation n instrumentation n automatic test equipment differential nonlinearity (ltc2601) 7 10 1 dac register input register 32-bit shift register 12-/14-/16-bit dac v out control decode logic ldac sdo 2 sdi sck 5 cs /ld 9 v cc 6 ref 8 gnd 2601 ta01a 4 clr 3 code 0 16384 32768 49152 65535 dnl (lsb) 2600 ta01b 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v
ltc2601/ltc2611/ltc2621 2 2601fb pin configuration absolute maximum ratings any pin to gnd ............................................ C0.3v to 6v any pin to v cc .............................................. C6v to 0.3v maximum junction temperature........................... 125c storage temperature range ................... C65c to 125c lead temperature (soldering, 10 sec) .................. 300c operating temperature range: ltc2601c/ltc2611c/ltc2621c ltc2601c-1/ltc2611c-1/ltc2621c-1 .... 0c to 70c ltc2601i/ltc2611i/ltc2621i ltc2601i-1/ltc2611i-1/ltc2621i-1 .... C40c to 85c (note 1) top view 11 dd package 10-lead (3mm s 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 lda c v cc gnd v out ref sdo sdi sck clr cs /ld t jmax = 125c, ja = 43c/w exposed pad (pin 11) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc2601cdd#pbf ltc2601cdd#trpbf lagt 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2601idd#pbf ltc2601idd#trpbf lagt 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2611cdd#pbf ltc2611cdd#trpbf lbfq 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2611idd#pbf ltc2611idd#trpbf lbfq 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2621cdd#pbf ltc2621cdd#trpbf lbfs 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2621idd#pbf ltc2621idd#trpbf lbfs 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2601cdd-1#pbf ltc2601cdd-1#trpbf lbzh 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2601idd-1#pbf ltc2601idd-1#trpbf lbzh 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2611cdd-1#pbf ltc2611cdd-1#trpbf lbzj 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2611idd-1#pbf ltc2611idd-1#trpbf lbzj 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2621cdd-1#pbf ltc2621cdd-1#trpbf lbzk 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2621idd-1#pbf ltc2621idd-1#trpbf lbzk 10-lead (3mm 3mm) plastic dfn C40c to 85c lead based finish tape and reel part marking* package description temperature range ltc2601cdd ltc2601cdd#tr lagt 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2601idd ltc2601idd#tr lagt 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2611cdd ltc2611cdd#tr lbfq 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2611idd ltc2611idd#tr lbfq 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2621cdd ltc2621cdd#tr lbfs 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2621idd ltc2621idd#tr lbfs 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2601cdd-1 ltc2601cdd-1#tr lbzh 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2601idd-1 ltc2601idd-1#tr lbzh 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2611cdd-1 ltc2611cdd-1#tr lbzj 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2611idd-1 ltc2611idd-1#tr lbzj 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc2621cdd-1 ltc2621cdd-1#tr lbzk 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2621idd-1 ltc2621idd-1#tr lbzk 10-lead (3mm 3mm) plastic dfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc2601/ltc2611/ltc2621 3 2601fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.5v), v out unloaded, unless otherwise noted. symbol param eter conditions ltc2621/ ltc2621-1 ltc2611/ ltc2611-1 ltc2601/ ltc2601-1 units min typ max min typ max min typ max dc performance resolution l 12 14 16 bits monotonicity (note 2) l 12 14 16 bits dnl differential nonlinearity (note 2) l 0.5 1 1 lsb inl integral nonlinearity (note 2) l 0.8 4 3 16 13 64 lsb load regulation v ref = v cc = 5v, midscale i out = 0ma to 15ma sourcing i out = 0ma to 15ma sinking l l 0.03 0.04 0.125 0.125 0.10 0.15 0.5 0.5 0.45 0.60 2 2 lsb/ma lsb/ma v ref = v cc = 2.5v, midscale i out = 0ma to 7.5ma sourcing i out = 0ma to 7.5ma sinking l l 0.06 0.08 0.25 0.25 0.2 0.3 1 1 0.9 1.2 4 4 lsb/ma lsb/ma zse zero-scale error code = 0 l 19 19 19 mv v os offset error (note 5) l 1.5 9 1.5 9 1.5 9 mv v os temperature coef? cient 5 5 5 v/c ge gain error l 0.03 0.7 0.1 0.7 0.05 0.7 %fsr gain temperature coef? cient 2 2 2 ppm/c the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.5v), v out unloaded, unless otherwise noted. (note 8) symbol parameter conditions min typ max units psr power supply rejection v cc = 5v 10% v cc = 3v 10% l C80 C80 db db r out dc output impedance v ref = v cc = 5v, midscale; C15ma i out 15ma v ref = v cc = 2.5v, midscale; C7.5ma i out 7.5ma l l 0.04 0.05 0.15 0.15 i sc short-circuit output current v cc = 5.5v, v ref = 5.5v code: zero scale; forcing output to v cc code: full scale; forcing output to gnd l l 15 15 35 39 60 60 ma ma v cc = 2.5v, v ref = 2.5v code: zero scale; forcing output to v cc code: full scale; forcing output to gnd l l 7.5 7.5 20 27 50 50 ma ma reference input input voltage range l 0 vcc v resistance normal mode l 88 124 160 k capacitance 15 pf i ref reference current, power down mode dac powered down l 0.001 1 a power supply v cc positive supply voltage for speci? ed performance l 2.5 5.5 v i cc supply current v cc = 5v (note 3) v cc = 3v (note 3) dac powered down (note 3) v cc = 5v dac powered down (note 3) v cc = 3v l l l l 0.375 0.30 0.40 0.10 0.55 0.45 1 1 ma ma a a digital i/o v ih digital input high voltage v cc = 2.5v to 5.5v v cc = 2.5v to 3.6v l l 2.4 2.0 v v
ltc2601/ltc2611/ltc2621 4 2601fb symbol parameter conditions min typ max units v il digital input low voltage v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v l l 0.8 0.6 v v v oh digital output high voltage load current = C100a l v cc C 0.4 v v ol digital output low voltage load current = +100a l 0.4 v i lk digital input leakage v in = gnd to v cc l 1 a c in digital input capacitance (note 4) l 8pf electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.5v), v out unloaded, unless otherwise noted. (note 8) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.5v), v out unloaded, unless otherwise noted. symbol param eter conditions ltc2621/ ltc2621-1 ltc2611/ ltc2611-1 ltc2601/ ltc2601-1 units min typ max min typ max min typ max ac performance t s settling time (note 6) 0.024% (1lsb at 12 bits) 0.006% (1lsb at 14 bits) 0.0015% (1lsb at 16 bits) 77 9 7 9 10 s s s settling time for 1lsb step (note 7) 0.024% (1lsb at 12 bits) 0.006% (1lsb at 14 bits) 0.0015% (1lsb at 16 bits) 2.7 2.7 4.8 2.7 4.8 5.2 s s s voltage output slew rate 0.80 0.80 0.80 v/s capacitive load driving 1000 1000 1000 pf glitch impulse at midscale transition 12 12 12 nv ? s multiplying bandwidth 180 180 180 khz e n output voltage noise density at f = 1khz at f = 10khz 120 100 120 100 120 100 nv/ hz nv/ hz output voltage noise 0.1hz to 10hz 15 15 15 v p-p timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (see figure 1) (notes 4, 8) symbol parameter conditions min typ max units v cc = 2.5v to 5.5v t 1 sdi valid to sck setup l 4ns t 2 sdi valid to sck hold l 4ns t 3 sck high time l 9ns t 4 sck low time l 9ns t 5 cs /ld pulse width l 10 ns t 6 lsb sck high to cs /ld high l 7ns t 7 cs /ld low to sck high l 7ns t 8 sdo propagation delay from sck falling edge c load = 10pf v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v l l 20 45 ns ns t 9 clr pulse width l 20 ns t 10 cs /ld high to sck positive edge l 7ns t 12 ldac pulse width l 15 ns t 13 cs /ld high to ldac high or low transition l 200 ns sck frequency 50% duty cycle l 50 mhz
ltc2601/ltc2611/ltc2621 5 2601fb typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature dnl vs temperature inl vs v ref dnl vs v ref timing characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: linearity and monotonicity are de? ned from code k l to code 2 n C 1, where n is the resolution and k l is given by k l = 0.016(2 n /v ref ), rounded to the nearest whole code. for v ref = 4.096v and n = 16, k l = 256 and linearity is de? ned from code 256 to code 65,535. note 3: digital inputs at 0v or v cc . note 4: guaranteed by design and not production tested. note 5: inferred from measurement at code k l = 0.016(2 n /v ref ) and at full scale. note 6: v cc = 5v, v ref = 4.096v. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 200pf to gnd. note 7: v cc = 5v, v ref = 4.096v. dac is stepped 1lsb between half scale and half scale C 1. load is 2k in parallel with 200pf to gnd. note 8: these speci? cations apply to ltc2601/ltc2601-1, ltc2611/ltc2611-1, ltc2621/ltc2621-1 ltc2601 code 0 16384 32768 49152 65535 inl (lsb) 2601 g01 32 24 16 8 0 ?8 ?16 ?24 ?32 v cc = 5v v ref = 4.096v code 0 16384 32768 49152 65535 dnl (lsb) 2600 g02 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v temperature (c) C50 C30 C10 10 30 50 70 90 inl (lsb) 2601 g03 32 24 16 8 0 C8 C16 C24 C32 v cc = 5v v ref = 4.096v inl (pos) inl (neg) temperature (c) C50 C30 C10 10 30 50 70 90 dnl (lsb) 2601 g04 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v dnl (pos) dnl (neg) v ref (v) 0 1 2 3 4 5 inl (lsb) 2601 g05 32 24 16 8 0 C8 C16 C24 C32 v cc = 5.5v inl (pos) inl (neg) v ref (v) 0 1 2 3 4 5 dnl (lsb) 2601 g06 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 v cc = 5.5v dnl (pos) dnl (neg)
ltc2601/ltc2611/ltc2621 6 2601fb 2s/div 2601 g07 v out 100v/div cs /ld 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 9.7s 5s/div 2601 g08 v out 100v/div cs /ld 2v/div settling to 1lsb v cc = 5v, v ref = 4.096v code 512 to 65535 step average of 2048 events 12.3s typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb settling to 1lsb settling of full-scale step ltc2601 ltc2621 ltc2611 code 0 4096 8192 12288 16383 inl (lsb) 2601 g09 8 6 4 2 0 C2 C4 C6 C8 v cc = 5v v ref = 4.096v code 0 4096 8192 12288 16383 dnl (lsb) 2601 g10 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v cc = 5v v ref = 4.096v 2s/div 2601 g11 v out 100v/div cs /ld 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 8.9s code 0 1024 2048 3072 4095 inl (lsb) 2601 g12 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 v cc = 5v v ref = 4.096v code 0 1024 2048 3072 4095 dnl (lsb) 2601 g13 v cc = 5v v ref = 4.096v 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 2s/div 2601 g14 v out 1mv/div cs /ld 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 6.8s
ltc2601/ltc2611/ltc2621 7 2601fb typical performance characteristics zero-scale error vs temperature gain error vs temperature offset error vs v cc gain error vs v cc i cc shutdown vs v cc large-signal response current limiting load regulation offset error vs temperature ltc2601/ltc2611/ltc2621 i out (ma) C40 C30 C20 C10 0 10 20 30 40 v out (v) 2601 g17 0.10 0.08 0.06 0.04 0.02 0 C0.02 C0.04 C0.06 C0.08 C0.10 v ref = v cc = 5v v ref = v cc = 3v v ref = v cc = 5v v ref = v cc = 3v code = midscale i out (ma) C35 C25 C15 C5 5 15 25 35 v out (mv) 2601 g18 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v ref = v cc = 5v code = midscale v ref = v cc = 3v temperature (c) C50 C30 C10 10 30 50 70 90 offset error (mv) 2601 g19 3 2 1 0 C1 C2 C3 temperature (c) C50 C30 C10 10 30 50 70 90 zero-scale error (mv) 2601 g20 3 2.5 2.0 1.5 1.0 0.5 0 temperature (c) C50 C30 C10 10 30 50 70 90 gain error (%fsr) 2601 g21 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 gain error (%fsr) 2601 g23 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 offset error (mv) 2601 g22 3 2 1 0 C1 C2 C3 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 i cc (na) 2601 g24 450 400 350 300 250 200 150 100 50 0 2.5s/div v out 0.5v/div 2601 g25 v ref = v cc = 5v 1/4-scale to 3/4-scale
ltc2601/ltc2611/ltc2621 8 2601fb typical performance characteristics supply current vs logic voltage hardware clr to zero scale hardware clr to midscale power-on reset to midscale multiplying bandwidth output voltage noise, 0.1hz to 10hz midscale glitch impulse power-on reset glitch to zero scale headroom at rails vs output current ltc2601/ltc2611/ltc2621 v out 10mv/div cs/ld 5v/div 2.5s/div 2601 g26 12nv-s typ v out 10mv/div 250s/div 2601 g27 v cc 1v/div 4mv peak i out (ma) 0 1 2 3 4 5 6 7 8 910 v out (v) 2601 g28 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5v sourcing 3v sourcing 3v sinking 5v sinking logic voltage (v) 0 0 i cc (ma) 0.2 0.6 0.8 1.0 1.4 0.5 2.5 3.5 2601 g29 0.4 1.2 2 4.5 5 1 1.5 34 v cc = 5v sweep sck, sdi and cs /ld 0v to v cc v out 1v/div 1s/div 2601 g31 clr 5v/div v cc = 5v v ref = 4.096v code = full scale v out 1v/div 1s/div 2601 g34 clr 5v/div v cc = 5v v ref = 4.096v code = full scale 1v/div v ref = v cc v cc v out 500s/div 2601 g35 frequency (hz) 1k db 0 C3 C6 C9 C12 C15 C18 C21 C24 C27 C30 C33 C36 1m 2601 g32 10k 100k v cc = 5v v ref (dc) = 2v v ref (ac) = 0.2v p-p code = full scale v out 10v/div seconds 012345678910 2601 g33
ltc2601/ltc2611/ltc2621 9 2601fb pin functions sdo (pin 1): serial interface data output. this pin is used for daisy-chain operation. the serial output of the shift register appears at the sdo pin. the data transferred to the device via the sdi pin is delayed 32 sck rising edges before being output at the next falling edge. sdo is an active output and does not go high impedance even when cs /ld is taken to a logic high level. sdi (pin 2): serial interface data input. data is applied to sdi for transfer to the device at the rising edge of sck (pin 3). the ltc2601 accepts input word lengths of either 24 or 32 bits. sck (pin 3): serial interface clock input. cmos and ttl compatible. clr (pin 4): asynchronous clear input. a logic low at this level-triggered input clears all registers and causes the dac voltage outputs to drop to 0v for ltc2601/ltc2611/ ltc2621. a logic low at this input sets all registers to midscale code and causes the dac voltage outputs to go to midscale for ltc2601-1/ltc2611-1/ltc2621-1. cmos and ttl compatible. cs /ld (pin 5): serial interface chip select/load input. when cs /ld is low, sck is enabled for shifting data on sdi into the register. when cs /ld is taken high, sck is disabled and the speci? ed command (see table 1) is executed. ref (pin 6): reference voltage input. 0v v ref v cc . v out (pin 7): dac analog voltage output. the output range is 0v to v ref . gnd (pin 8): analog ground. v cc (pin 9): supply voltage input. 2.5v v cc 5.5v. ldac (pin 10): asynchronous dac update pin. if cs /ld is high, a falling edge on ldac immediately updates the dac register with the contents of the input register (similar to a software update). if cs /ld is low when ldac goes low, the dac register is updated after cs /ld returns high. a low on the ldac pin powers up the dac. a software power down command is ignored if ldac is low. exposed pad (pin 11): ground. must be soldered to pcb ground. typical performance characteristics short-circuit output current vs v out (sinking) short-circuit output current vs v out (sourcing) ltc2601/ltc2611/ltc2621 1v/div 0 0 10ma/div 10 20 30 40 50 1 234 2601 g15 56 v cc = 5.5v v ref = 5.6v code = 0 v out swept 0v to v cc 1v/div 0 C50 10ma/div C40 C30 C20 C10 0 1 234 2601 g16 56 v cc = 5.5v v ref = 5.6v code = full scale v out swept v cc to 0v
ltc2601/ltc2611/ltc2621 10 2601fb block diagram timing diagrams figure 1a figure 1b 7 10 1 dac register input register 32-bit shift register 12-/14-/16-bit dac v out control decode logic ldac sdo 2 sdi sck 5 cs /ld 9 v cc 6 ref 8 gnd 2601 bd 4 clr 3 sdi sdo c s /ld sck 2601 f01a t 2 t 8 t 10 t 5 t 7 t 6 t 1 ldac t 3 t 4 1232324 t 13 t 12 cs /ld 2601 f01b t 13 ldac
ltc2601/ltc2611/ltc2621 11 2601fb operation only be transferred to the device when the cs /ld signal is low.the rising edge of cs /ld ends the data transfer and causes the device to execute the command speci? ed in the 24-bit input word. the complete sequence is shown in figure 2a. the command (c3-c0) assignments are shown in table 1. the ? rst four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register of the dac. in an update operation, the data word is copied from the input register to the dac register and converted to an analog voltage at the dac output. the update operation also powers up the dac if it had been in power-down mode. the data path and registers are shown in the block diagram. while the minimum input word is 24 bits, it may option- ally be extended to 32 bits. to use the 32-bit word width, 8 dont-care bits are transferred to the device ? rst, followed by the 24-bit word as just described. figure 2b shows the 32-bit sequence. the 32-bit word is required for daisy- chain operation, and is also available to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). daisy-chain operation the serial output of the shift register appears at the sdo pin. data transferred to the device from the sdi input is delayed 32 sck rising edges before being output at the next sck falling edge. the sdo output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., sck, sdi and cs /ld). such a daisy chain series is con? gured by connecting sdo of each upstream device to sdi of the power-on reset the ltc2601/ltc2611/ltc2621 clear the outputs to zero scale when power is ? rst applied, making system initializa- tion consistent and repeatable. the ltc2601-1/ltc2611- 1/ltc2621-1 set the voltage outputs to midscale when power is ? rst applied. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2601/ ltc2611/ltc2621 contain circuitry to reduce the power- on glitch; furthermore, the glitch amplitude can be made arbitrarily small by reducing the ramp rate of the power supply. for example, if the power supply is ramped to 5v in 1ms, the analog outputs rise less than 10mv above ground (typ) during power-on. see power-on reset glitch in the typical performance characteristics section. power supply sequencing the voltage at ref (pin 6) should be kept within the range C0.3v v ref v cc + 0.3v (see absolute maximum rat- ings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc (pin 16) is in transition. transfer function the digital-to-analog transfer function is: v k v out ideal n ref () = ? ? ? ? ? ? 2 where k is the decimal equivalent of the binary dac input code, n is the resolution and v ref is the voltage at ref (pin 6). serial interface the cs /ld input is level triggered. when this input is taken low, it acts as a chip-select signal, powering-on the sdi and sck buffers and enabling the input shift register. data (sdi input) is transferred at the next 24 rising sck edges. the 4-bit command, c3-c0, is loaded ? rst; then 4 dont care bits; and ? nally the 16-bit data word. the data word comprises the 16-, 14- or 12-bit input code, ordered msb-to-lsb, followed by 0, 2 or 4 dont care bits (ltc2601, ltc2611 and ltc2621 respectively). data can table 1. command* c3 c2 c1 c0 0 0 0 0 write to input register 0 0 0 1 update (power up) dac register 0 0 1 1 write to and update (power up) 0 1 0 0 power down 1 1 1 1 no operation *command codes not shown are reserved and should not be used.
ltc2601/ltc2611/ltc2621 12 2601fb operation next device in the chain. the shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the ? rst instruction addresses the last device in the chain and so forth. the sck and cs /ld signals are common to all devices in the series. in use, cs /ld is ? rst taken low. then the concatenated input data is transferred to the chain, using sdi of the ? rst device as the data input. when the data transfer is complete, cs /ld is taken high, which executes the com- mands speci? ed for each of the devices simultaneously. a single device can be controlled by using the no-operation command (1111) for the other devices in the chain. power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever the dac output is not needed. when in power-down, the buffer ampli? er, bias circuit and reference input is disabled and draws essentially zero current. the dac output is put into a high impedance state, and the output pin is passively pulled to ground through 90k resistors. input- and dac-register contents are not disturbed during power-down. the dac can be put into power-down mode by using command 0100 b . the 16-bit data word is ignored. the supply and reference currents are reduced to almost zero when the dac is powered down; the effective resistance at ref rises accordingly becoming a high impedance input (typically > 1g). normal operation can be resumed by executing any com- mand which includes a dac update, as shown in table 1 or performing an asynchronous update ( ldac ) as described in the next section. the dac is powered up as its voltage output is updated. when the dac in powered-down state is powered up and updated, normal settling is delayed. the main bias generation circuit block has been automatically shut down in addition to the dac ampli? er and reference input and so the power up delay time is 12s (for v cc = 5v) or 30s (for v cc = 3v). asynchronous dac update using ldac in addition to the update commands shown in table 1, the ldac pin asynchronously updates the dac register with the contents of the input register. if cs /ld is high, a low on the ldac pin causes the dac register to be updated with the contents of the input register. if cs /ld is low, a low going pulse on the ldac pin before the rising edge of cs /ld powers up the dac but does not cause the output to be updated. if ldac remains low after input word (ltc2601) input word (ltc2611) input word (ltc2621) c3 command dont care bits data (16 bits) c2 c1 c0 x x x x d13 d14 d15 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 2601 tbl01 msb lsb c3 command dont care bits data (14 bits + 2 dont care bits) c2 c1 c0 x x x x d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x 2601 tbl02 msb lsb c3 command dont care bits data (12 bits + 4 dont care bits) c2 c1 c0 x x x x d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x xx 2601 tbl03 msb lsb
ltc2601/ltc2611/ltc2621 13 2601fb the rising edge of cs /ld, then ldac is recognized, the command speci? ed in the 24-bit word just transferred is executed and the dac output is updated. the dac is powered up when ldac is taken low, inde- pendent of the state of cs /ld. if ldac is low at the time cs /ld goes high, it inhibits any software power-down command that was speci? ed in the input word. voltage outputs the rail-to-rail ampli? er contained in these parts has guaranteed load regulation when sourcing or sinking up to 15ma at 5v (7.5ma at 3v). load regulation is a measure of the ampli? ers ability to maintain the rated voltage accuracy over a wide range of load conditions. the measured change in output voltage per milliampere of forced load current change is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the ampli? ers dc output impedance is 0.05 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices; e.g., when sinking 1ma, the minimum output voltage = 25 ? 1ma = 25mv. see the graph headroom at rails vs output current in the typical performance characteristics section. the ampli? er is stable driving capacitive loads of up to 1000pf. board layout the excellent load regulation of these devices is achieved in part by keeping signal and power grounds separated internally and by reducing shared internal resistance. the gnd pin functions both as the node to which the refer- ence and output voltages are referred and as a return path operation for power currents in the device. because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. the pc board should have separate areas for the analog and digital sections of the circuit. this keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the devices ground pin as possible. ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. the gnd pin of the part should be connected to analog ground. resistance from the gnd pin to system star ground should be as low as possible. resistance here will add directly to the effective dc output impedance of the device (typically 0.05). note that the ltc2601/ ltc2611/ltc2621 are no more susceptible to these ef- fects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog output of the device cannot go below ground, it may limit for the lowest codes as shown in figure 3b. similarly, limiting can occur near full scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 3c. no full-scale limiting can occur if v ref is less than v cc C fse. offset and linearity are de? ned and tested over the region of the dac transfer function where no output limiting can occur.
ltc2601/ltc2611/ltc2621 14 2601fb operation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 x x x x d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 cs /ld sck sdi command word 4 dont care bits data word 24-bit input word 2601 f02a figure 2b. ltc2601 32-bit load sequence (required for daisy-chain operation). ltc2611 sdi/sdo data word: 14-bit input code + 2 dont-care bits; ltc2621 sdi/sdo data word: 12-bit input code + 4 dont-care bits figure 2a. ltc2601 24-bit load sequence (minimum input word). ltc2611 sdi data word: 14-bit input code + 2 dont-care bits; ltc2621 sdi data word: 12-bit input code + 4 dont-care bits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 x x x x d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x cs /ld sck sdi command word data word dont care 4 dont care bits c2 c1 c0 x x x x d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x sdo current 32-bit input word 2601 f02b previous 32-bit input word t 2 t 3 t 4 t 1 t 8 d15 17 sck sdi sdo previous d14 previous d15 18 d14
ltc2601/ltc2611/ltc2621 15 2601fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.3 8 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.3 8 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd10) dfn 1103 0.25 0.05 2.3 8 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc package description figure 3. effects of rail-to-rail operation on the dac transfer curve. (a) overall transfer function (b) effect of negative offset for codes near zero scale (c) effect of positive full-scale error for codes near full scale 2601 f03 input code (b) output voltage negative offset 0v 32, 768 0 65, 535 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positive fse operation dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699)
ltc2601/ltc2611/ltc2621 16 2601fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0409 rev b ? printed in usa related parts typical application demo circuit dc777 schematic. onboard 20-bit adc measures key performance parameters ldac clr sdi sck cs /ld sdo sck sdo cs f o 9 8 7 10 10 4 2 3 5 1 7 56 2 96 1 2601 ta02 3 100 7.5k 0.1f 8 v out v cc spi bus ltc2601 gnd 5v v ref 1v to 5v dac output v ref v cc gnd v in ltc2421 fs set zs set 0.1f 5v 100pf part number description comments ltc1458/ltc1458l quad 12-bit rail-to-rail output dacs with added functionality ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.096v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1654 dual 14-bit rail-to-rail v out dac programmable speed/power, 3.5s/750a, 8s/450a ltc1655/ltc1655l single 16-bit v out dacs with serial interface in so-8 v cc = 5v(3v), low power, deglitched ltc1657/ltc1657l parrallel 5v/3v 16-bit v out dacs low power, deglitched, rail-to-rail v out ltc1660/ltc1665 octal 10/8-bit v out dacs in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1661 dual 10-bit v out dac 8-lead msop micropower rail-to-rail output, 3-wire interface ltc1662 dual 10-bit v out dac 8-lead msop ultralow power, rail-to-rail output ltc1663 single 10-bit v out dac in sot-23 smbus interface, pin-for-pin compatible with ltc1669 ltc1664 quad 10-bit v out dac 16-lead ssop micropower rail-to-rail output, 3-wire interface ltc1669 single 10-bit v out dac 5-lead sot-23 pin-for-pin compatible with ltc1663 ltc1821 parallel 16-bit voltage output dac precision 16-bit settling in 2s for 10v step ltc2600/ltc2610/ ltc2620 octal 16-bit/14-bit/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output ltc2602/ltc2612/ ltc2622 dual 16-bit/14-bit/12-bit v out dacs in 8-lead msop 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output ltc2604/ltc2614/ ltc2624 quad 16-bit/14-bit/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2605/ltc2615/ ltc2625 octal 16-bit/14-bit/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output, i 2 c interface ltc2606/ltc2616/ ltc2626 16-bit/14-bit/12-bit v out dacs with i 2 c interface 270a per dac, 2.7v to 5.5v supply range, rail-to-rail output, i 2 c interface ltc2607/ltc2617/ ltc2627 dual 16-bit/14-bit/12-bit v out dacs in 12-lead dfn with i 2 c interface 260a per dac, 2.7v to 5.5v supply range, rail-to-rail output, i 2 c interface ltc2609/ltc2619/ ltc2629 quad 16-bit/14-bit/12-bit v out dacs with i 2 c interface 250a range per dac, 2.7v to 5.5v supply range, rail-to-rail output with separate v ref pins for each dac

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